/*
 * Copyright (C) 2017 Spreadtrum Communications Inc.
 *
 * This file is dual-licensed: you can use it either under the terms
 * of the GPL or the X11 license, at your option. Note that this dual
 * licensing only applies to this file, and not this project as a
 * whole.
 *
 * updated at 2017-12-14 16:29:52
 *
 */


#ifndef ANLG_PHY_G12_H
#define ANLG_PHY_G12_H

#define CTL_BASE_ANLG_PHY_G12 0x32430000


#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_PWR_CTRL       ( CTL_BASE_ANLG_PHY_G12 + 0x0000 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_RST_CTRL       ( CTL_BASE_ANLG_PHY_G12 + 0x0004 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_EN_CTRL        ( CTL_BASE_ANLG_PHY_G12 + 0x0008 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL2           ( CTL_BASE_ANLG_PHY_G12 + 0x000C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL2            ( CTL_BASE_ANLG_PHY_G12 + 0x0010 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL0           ( CTL_BASE_ANLG_PHY_G12 + 0x0014 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL1           ( CTL_BASE_ANLG_PHY_G12 + 0x0018 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_BIST_CTRL       ( CTL_BASE_ANLG_PHY_G12 + 0x001C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL0            ( CTL_BASE_ANLG_PHY_G12 + 0x0020 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL1            ( CTL_BASE_ANLG_PHY_G12 + 0x0024 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_BIST_CTRL        ( CTL_BASE_ANLG_PHY_G12 + 0x0028 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL0            ( CTL_BASE_ANLG_PHY_G12 + 0x002C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL1            ( CTL_BASE_ANLG_PHY_G12 + 0x0030 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL2            ( CTL_BASE_ANLG_PHY_G12 + 0x0034 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_BIST_CTRL        ( CTL_BASE_ANLG_PHY_G12 + 0x0038 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TEST_CLK_CTRL         ( CTL_BASE_ANLG_PHY_G12 + 0x003C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_0           ( CTL_BASE_ANLG_PHY_G12 + 0x0040 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_WRAP_GLUE_CTRL        ( CTL_BASE_ANLG_PHY_G12 + 0x0044 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_1           ( CTL_BASE_ANLG_PHY_G12 + 0x0048 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_2           ( CTL_BASE_ANLG_PHY_G12 + 0x004C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_3           ( CTL_BASE_ANLG_PHY_G12 + 0x0050 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_4           ( CTL_BASE_ANLG_PHY_G12 + 0x0054 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_CAL             ( CTL_BASE_ANLG_PHY_G12 + 0x0058 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_CAL              ( CTL_BASE_ANLG_PHY_G12 + 0x005C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_CAL              ( CTL_BASE_ANLG_PHY_G12 + 0x0060 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_CAL              ( CTL_BASE_ANLG_PHY_G12 + 0x0064 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_FREQ_CAL_CFG      ( CTL_BASE_ANLG_PHY_G12 + 0x0068 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_RESULT          ( CTL_BASE_ANLG_PHY_G12 + 0x006C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_RESULT           ( CTL_BASE_ANLG_PHY_G12 + 0x0070 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_RESULT           ( CTL_BASE_ANLG_PHY_G12 + 0x0074 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_RESULT           ( CTL_BASE_ANLG_PHY_G12 + 0x0078 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_TEST_FLAG         ( CTL_BASE_ANLG_PHY_G12 + 0x007C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL0          ( CTL_BASE_ANLG_PHY_G12 + 0x0080 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL1          ( CTL_BASE_ANLG_PHY_G12 + 0x0084 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL2          ( CTL_BASE_ANLG_PHY_G12 + 0x0088 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL3          ( CTL_BASE_ANLG_PHY_G12 + 0x008C )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_RESERVED          ( CTL_BASE_ANLG_PHY_G12 + 0x0090 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_RESERVED        ( CTL_BASE_ANLG_PHY_G12 + 0x0098 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_RESERVED         ( CTL_BASE_ANLG_PHY_G12 + 0x00A0 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_RESERVED         ( CTL_BASE_ANLG_PHY_G12 + 0x00A8 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_RESERVED       ( CTL_BASE_ANLG_PHY_G12 + 0x00B0 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_PERFOR          ( CTL_BASE_ANLG_PHY_G12 + 0x00B8 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_PERFOR           ( CTL_BASE_ANLG_PHY_G12 + 0x00BC )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_PERFOR           ( CTL_BASE_ANLG_PHY_G12 + 0x00C0 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_PERFOR         ( CTL_BASE_ANLG_PHY_G12 + 0x00C4 )
#define REG_ANLG_PHY_G12_ANALOG_PLL_TOP_REG_SEL_CFG_0         ( CTL_BASE_ANLG_PHY_G12 + 0x00C8 )

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_PWR_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_PD                BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_PD                 BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_PD                 BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_PD               BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_RST_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_RST               BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_RST                BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_RST                BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_RST              BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ANA_BB_EN_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CLKOUT_EN          BIT(26)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_DIV1_EN          BIT(25)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_DIV2_EN          BIT(24)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_DIV3_EN          BIT(23)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CLKOUT_EN        BIT(22)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ANALOG_TESTMUX(x)       (((x) & 0xFFFF) << 6)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_POSTDIV            BIT(5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_POSTDIV           BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_OD_TWPLL_CLKOUT_EN      BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_OD_LPLL_CLKOUT_EN       BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_OD_GPLL_CLKOUT_EN       BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_OD_ISPPLL_CLKOUT_EN     BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL2 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CLKOUT_EN         BIT(6)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV1_EN           BIT(5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV2_EN           BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV3_EN           BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV5_EN           BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV7_EN           BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_LOCK_DONE         BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL2 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CLKOUT_EN          BIT(5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_DIV1_EN            BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_DIV2_EN            BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_DIV3_EN            BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_DIV5_EN            BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_LOCK_DONE          BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL0 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_N(x)              (((x) & 0x7FF) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_IBIAS(x)          (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_LPF(x)            (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_SDM_EN            BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_MOD_EN            BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_DIV_S             BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_REF_SEL(x)        (((x) & 0x3))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CTRL1 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_NINT(x)           (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_KINT(x)           (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_BIST_EN           BIT(24)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_BIST_CTRL(x)      (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_BIST_CNT(x)       (((x) & 0xFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL0 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_N(x)               (((x) & 0x7FF) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_IBIAS(x)           (((x) & 0x3) << 8)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_LPF(x)             (((x) & 0x7) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_SDM_EN             BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_MOD_EN             BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_DIV_S              BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_REF_SEL(x)         (((x) & 0x3))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CTRL1 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_BIST_EN            BIT(24)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_BIST_CTRL(x)       (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL0 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_N(x)               (((x) & 0x7FF) << 9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_IBIAS(x)           (((x) & 0x3) << 7)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_LPF(x)             (((x) & 0x7) << 4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_SDM_EN             BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_MOD_EN             BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_DIV_S              BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_REF_SEL            BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL1 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_NINT(x)            (((x) & 0x7F) << 23)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_KINT(x)            (((x) & 0x7FFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CTRL2 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_POSTDIV            BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_LOCK_DONE          BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_BIST_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_BIST_EN            BIT(24)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_BIST_CTRL(x)       (((x) & 0xFF) << 16)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_BIST_CNT(x)        (((x) & 0xFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TEST_CLK_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TEST_CLK_EN             BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TEST_CLK_DIV(x)         (((x) & 0x3))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_0 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_MAX_RANGE(x)       (((x) & 0x3FFF) << 17)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_MIN_RANGE(x)       (((x) & 0x3FFF) << 3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_RSTN               BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_GEN_SEL(x)         (((x) & 0x3))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_WRAP_GLUE_CTRL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_STEP_SEL           BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_1 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D0(x)         (((x) & 0x3FFF) << 14)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D1(x)         (((x) & 0x3FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_2 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D2(x)         (((x) & 0x3FFF) << 14)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D3(x)         (((x) & 0x3FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_3 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D4(x)         (((x) & 0x3FFF) << 14)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D5(x)         (((x) & 0x3FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_TEST_4 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D6(x)         (((x) & 0x3FFF) << 14)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AAPC_SQUA_D7(x)         (((x) & 0x3FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_CAL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_MAX_RANGE(x)      (((x) & 0x7FFF) << 15)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_MIN_RANGE(x)      (((x) & 0x7FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_CAL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_MAX_RANGE(x)       (((x) & 0x7FFF) << 15)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_MIN_RANGE(x)       (((x) & 0x7FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_CAL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_MAX_RANGE(x)       (((x) & 0x7FFF) << 15)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_MIN_RANGE(x)       (((x) & 0x7FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_CAL */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_MAX_RANGE(x)       (((x) & 0x7FFF) << 15)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_MIN_RANGE(x)       (((x) & 0x7FFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_FREQ_CAL_CFG */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_DIV_NUM_26M(x)          (((x) & 0x3FF) << 4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_CAL_EN             BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_CAL_EN             BIT(2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_CAL_EN             BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_CAL_EN            BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_RESULT */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_FREQ(x)           (((x) & 0x7FFF) << 2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_READY             BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PROBE_PASS              BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_RESULT */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_FREQ(x)            (((x) & 0x7FFF) << 2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_READY              BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX0_PASS               BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_RESULT */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_FREQ(x)            (((x) & 0x7FFF) << 2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_READY              BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX1_PASS               BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_RESULT */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_FREQ(x)            (((x) & 0x7FFF) << 2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_READY              BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_AUX2_PASS               BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_TEST_FLAG */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_PLLS_FLAG(x)            (((x) & 0xFFFFFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL0 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_N(x)             (((x) & 0x7FF) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_IBIAS(x)         (((x) & 0x3) << 3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_LPF(x)           (((x) & 0x7))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL1 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_NINT(x)          (((x) & 0x7F) << 25)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_KINT(x)          (((x) & 0x7FFFFF) << 2)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_SDM_EN           BIT(1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_MOD_EN           BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL2 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_DIV_S            BIT(11)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_REF_SEL          BIT(10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_BIST_EN          BIT(9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_BIST_CTRL(x)     (((x) & 0xFF) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_POSTDIV          BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CTRL3 */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_BIST_CNT(x)      (((x) & 0xFFFF) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_LOCK_DONE        BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_PLL_RESERVED */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ANALOG_PLL_RESERVED(x)  (((x) & 0x3FFFFFFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_RESERVED */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_SSC_CTRL(x)       (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_RESERVED(x)       (((x) & 0x7FF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_RESERVED */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_SSC_CTRL(x)        (((x) & 0xFF) << 11)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_RESERVED(x)        (((x) & 0x7FF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_RESERVED */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_RESERVED(x)        (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_SSC_CTRL(x)        (((x) & 0xFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_RESERVED */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_RESERVED(x)      (((x) & 0x7FF) << 8)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_SSC_CTRL(x)      (((x) & 0xFF))

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_PERFOR */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_ICP(x)            (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CP_EN             BIT(9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_LDO_TRIM(x)       (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_VCO_TEST_EN       BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_FBDIV_EN          BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_CP_OFFSET(x)      (((x) & 0x3) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_TWPLL_FREQ_DOUBLE_EN    BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_PERFOR */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_ICP(x)             (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CP_EN              BIT(9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_LDO_TRIM(x)        (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_VCO_TEST_EN        BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_FBDIV_EN           BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_CP_OFFSET(x)       (((x) & 0x3) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_LPLL_FREQ_DOUBLE_EN     BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_PERFOR */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_ICP(x)             (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CP_EN              BIT(9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_LDO_TRIM(x)        (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_VCO_TEST_EN        BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_FBDIV_EN           BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_CP_OFFSET(x)       (((x) & 0x3) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_GPLL_FREQ_DOUBLE_EN     BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_PERFOR */

#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_ICP(x)           (((x) & 0x7) << 10)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CP_EN            BIT(9)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_LDO_TRIM(x)      (((x) & 0xF) << 5)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_VCO_TEST_EN      BIT(4)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_FBDIV_EN         BIT(3)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_CP_OFFSET(x)     (((x) & 0x3) << 1)
#define BIT_ANLG_PHY_G12_ANALOG_PLL_TOP_ISPPLL_FREQ_DOUBLE_EN   BIT(0)

/* REG_ANLG_PHY_G12_ANALOG_PLL_TOP_REG_SEL_CFG_0 */

#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_PD        BIT(20)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_PD         BIT(19)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_GPLL_PD         BIT(18)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_PD       BIT(17)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_RST       BIT(16)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_RST        BIT(15)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_GPLL_RST        BIT(14)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_RST      BIT(13)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_GPLL_CLKOUT_EN  BIT(12)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_DIV2_EN  BIT(11)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_ISPPLL_DIV3_EN  BIT(10)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV1_EN   BIT(9)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV2_EN   BIT(8)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV3_EN   BIT(7)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_DIV5_EN   BIT(6)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV1_EN    BIT(5)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV2_EN    BIT(4)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV3_EN    BIT(3)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_DIV5_EN    BIT(2)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_TWPLL_REF_SEL   BIT(1)
#define BIT_ANLG_PHY_G12_DBG_SEL_ANALOG_PLL_TOP_LPLL_REF_SEL    BIT(0)


#endif /* ANLG_PHY_G12_H */


